1. Field of the Invention
The present invention relates to a semiconductor device and, in particular, to a semiconductor device having a transistor which has source regions and drain regions arranged adjoining each other with a grid-like gate electrode disposed therebetween.
2. Description of the Related Art
There is a conventionally known MOS transistor having a gate electrode formed in a grid pattern so as to raise the efficiency of the gate width (GW) per unit area. This MOS transistor is called a waffle transistor.
FIG. 1 shows a schematic plane composition of a conventional grid-like transistor 1. The grid-like transistor 1 has a gate electrode 2 formed in a grid pattern and diffusion regions surrounded by the gate electrode 2. The diffusion regions are each square-shaped, thereby raising the density of the circuit. The diffusion regions are each a source region 3 or a drain region 4, and the source region 3 and the drain region 4 are arranged alternately adjacent to each other with the gate electrode 2 disposed therebetween. Formed on the source region 3 and the drain region 4 are a source contact 5 and a drain contact 6, respectively, for connection to a metal wiring.
In the grid-like transistor 1, all the source regions 3 and all the drain regions 4 are connected to their common electrodes, respectively. In the grid-like transistor 1, the source contacts 5 are connected to a source metal wiring extending in a direction along the grid of the gate electrode 2, and the drain contacts 6 are connected to a drain metal wiring extending in the same direction along the grid of the gate electrode 2, in a first metal layer above a back-gate diffusion layer. In the first metal layer, the source metal wiring and the drain metal wiring are formed alternately with each other. In a second metal layer, which is above the first metal layer, a plurality of source metal wirings are connected to a common source electrode whereas a plurality of drain metal wirings are connected to a common drain electrode.
FIG. 2 shows an example of schematic arrangement of metal wirings in a first metal layer. As illustrated in FIG. 2, a source metal wiring 7 and a drain metal wiring 8 are formed in such a manner as to extend in the same direction along the grid of a gate electrode 2. And they are connected to source contacts 5 and drain contacts 6, respectively. Note, however, that the drain metal wirings 8 connecting to the drain contacts 6 on the upper and lower sides of the planar view are not shown in FIG. 2.
The source metal wiring 7 and the drain metal wiring 8 have each a form composed of a thin rectangular region, which is so formed as to cover top of the gate electrode 2 extending in a length direction, and projecting regions, which protrude in a width direction from the rectangular region to be connected to the contact in each diffusion region. As shown in FIG. 2, therefore, the width of the metal wiring is greater where there is the projecting region and smaller where there is not. Especially when the diffusion regions are formed at a highest density, there occur instances where diagonal wiring cannot be made due to layout limitations. Thus, variation of the width of the metal wiring in the length direction causes an increase in parasitic resistance in the narrow-width regions. The parasitic resistance of the metal wiring adds to the input/output resistance of the MOS transistor. The increase in the parasitic resistance is not desirable because it will result in an increase in overall on-resistance, which is a combination of the on-resistance of the transistor and the parasitic resistance of the wiring, and a loss of drive capacity. The grid-like transistor has been introduced with the primary purpose of downsizing the circuit by raising the efficiency of the gate width (GW) per unit area, thereby reducing the on-resistance of the transistor and enhancing the drive capacity. However, this original advantage of the grid-like transistor can be lost if the overall on-resistance increases due to the increase in the metal wiring resistance.